
`include "common_header.verilog"

//  *************************************************************************
//  File : rs_64.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited.
//  Copyright (c) 2014 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Muhammad Anisur Rahman, Thomas Schrobenhauser
//  info@morethanip.com
//  *************************************************************************
//  Description : 40G MAC Reconciliation Sub-Layer
//  Version     : $Id: rs_64.v,v 1.6 2014/10/31 17:06:08 ts Exp $
//  *************************************************************************

module rs_64 (
   reset_rxclk,
   reset_txclk,
   enable_rx,
   xgmii_mode,
   force_send_idle,
   disable_flt_hdl,
   lowp_ena_t,
   xlgmii_rxclk,
   xlgmii_rxclk_ena,
   xlgmii_rxc,
   xlgmii_rxd,
   xlgmii_rxt0_next,
   xlgmii_txclk,
   xlgmii_txclk_ena,
   xlgmii_txc,
   xlgmii_txd,
   rx_d,
   rx_dval,
   rx_start,
   rx_end,
   rx_final_size,
   frame_err,
   phy_err,
   rs_fault,
   tx_val,
   tx_d,
   tx_final_size,
   tx_err,
   tx_end,
   tx_rsfault,
   lf_state,
   rf_state,
   li_state,
   tx_loc_fault,
   tx_rem_fault,
   tx_li_fault,
   rs_lowp
   );

input   reset_rxclk;                    //  Async active high reset
input   reset_txclk;                    //  Async active high reset
input   enable_rx;                      //  Enable state machines when PLLs are locked (rxclk)
input   xgmii_mode;                     //  XGMII mode enable (0=XLGMII, 1=XGMII)
input   force_send_idle;                //  force Idle send (async)
input   disable_flt_hdl;                //  if '1', RX RS does not affect TX data path
input   lowp_ena_t;                     //  Low Power Generation (sync'ed to txclk)
input   xlgmii_rxclk;                   //  XLGMII receive clock
input   xlgmii_rxclk_ena;               //  XLGMII receive clock enable
input   [7:0] xlgmii_rxc;               //  XLGMII receive control
input   [63:0] xlgmii_rxd;              //  XLGMII receive data
input   xlgmii_rxt0_next;               //  XLGMII terminate on lane 0 in next word
input   xlgmii_txclk;                   //  XLGMII transmit clock
input   xlgmii_txclk_ena;               //  XLGMII transmit clock enable
output  [7:0] xlgmii_txc;               //  XLGMII transmit control
output  [63:0] xlgmii_txd;              //  XLGMII transmit data
output  [63:0] rx_d;                    //  Receive data
output  rx_dval;                        //  Receive data valid
output  rx_start;                       //  Start of Frame
output  rx_end;                         //  End of Frame
output  [2:0] rx_final_size;            //  Define size of final data word
output  frame_err;                      //  Frame error received
output  phy_err;                        //  Control code error
output  rs_fault;                       //  Link fault sequence detected (any)
input   tx_val;                         //  XLGMII Transmit Data valid
input   [63:0] tx_d;                    //  XLGMII Transmit data
input   [2:0] tx_final_size;            //  XLGMII Transmit final data word size
input   tx_err;                         //  XLGMII Transmit Error
input   tx_end;                         //  Transmit last word on tx_d (eop)
output  tx_rsfault;                     //  Hold MAC TX as RS is in fault
output  lf_state;                       //  Local Fault Indication (rxclk)
output  rf_state;                       //  Remote Fault Indication (rxclk)
output  li_state;                       //  LinkInterruption Fault Indication (rxclk)
input   tx_loc_fault;                   //  Force TX LF (txclk)
input   tx_rem_fault;                   //  Force TX RF (txclk)
input   tx_li_fault;                    //  Force TX LI (txclk)
output  rs_lowp;                        //  Low Power Detection

wire    [7:0] xlgmii_txc;
wire    [63:0] xlgmii_txd;
wire    [63:0] rx_d;
wire    rx_dval;
wire    rx_start;
wire    rx_end;
wire    [2:0] rx_final_size;
wire    frame_err;
wire    phy_err;
wire    rs_fault;
wire    tx_rsfault;
wire    lf_state;
wire    rf_state;
wire    li_state;
wire    rs_lowp;

wire    lf_state_int;   //  Status from Receiver
wire    rf_state_int;   //  Status from Receiver
wire    li_state_int;   //  Status from Receiver


rs_rx_64 U_RSRX (
          .reset_rxclk(reset_rxclk),
          .enable_rx(enable_rx),
          .xgmii_mode(xgmii_mode),
          .xlgmii_rxclk(xlgmii_rxclk),
          .xlgmii_rxclk_ena(xlgmii_rxclk_ena),
          .xlgmii_rxc(xlgmii_rxc),
          .xlgmii_rxd(xlgmii_rxd),
          .xlgmii_rxt0_next(xlgmii_rxt0_next),
          .rx_d(rx_d),
          .rx_dval(rx_dval),
          .rx_start(rx_start),
          .rx_end(rx_end),
          .rx_final_size(rx_final_size),
          .frame_err(frame_err),
          .phy_err(phy_err),
          .rs_fault(rs_fault),
          .lf_state(lf_state_int),
          .rf_state(rf_state_int),
          .li_state(li_state_int),
          .rs_lowp(rs_lowp)
          );

assign lf_state = lf_state_int;
assign rf_state = rf_state_int;
assign li_state = li_state_int;


rs_tx_64 U_RSTX (
          .reset_txclk(reset_txclk),
          .xgmii_mode(xgmii_mode),
          .force_send_idle(force_send_idle),
          .disable_flt_hdl(disable_flt_hdl),
          .lowp_ena_t(lowp_ena_t),
          .xlgmii_txclk(xlgmii_txclk),
          .xlgmii_txclk_ena(xlgmii_txclk_ena),
          .xlgmii_txc(xlgmii_txc),
          .xlgmii_txd(xlgmii_txd),
          .tx_val(tx_val),
          .tx_d(tx_d),
          .tx_final_size(tx_final_size),
          .tx_err(tx_err),
          .tx_end(tx_end),
          .tx_rsfault(tx_rsfault),
          .lf_state(lf_state_int),
          .rf_state(rf_state_int),
          .li_state(li_state_int),
          .tx_loc_fault(tx_loc_fault),
          .tx_rem_fault(tx_rem_fault),
          .tx_li_fault(tx_li_fault)
          );


endmodule // module rs_64
